technical data 39 14 stage ripple-carry binary counter/divider high-voltage silicon-gate cmos the iw4020b is ripple-carry binary counter. all counter stages are master-slave flip-flops. the state of a counter advances one count on the negative transition of each input pulse; a high level on the reset line resets the counter to its all zeros state. schmitt trigger action on the input-pulse line permits unlimited rise and fall times. ? operating voltage range: 3.0 to 18 v ? maximum input current of 1 a at 18 v over full package- temperature range; 100 na at 18 v and 25 c ? noise margin (over full package temperature range): 1.0 v min @ 5.0 v supply 2.0 v min @ 10.0 v supply 2.5 v min @ 15.0 v supply iw4020b ordering information iw4020bn plastic IW4020BDW soic t a = -55 to 125 c for all packages logic diagram pin 16 =v cc pin 8 = gnd pin assignment function table inputs output clock reset output state l no change l advance to next state x h all outputs are low x=don?t care
iw4020b 40 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +20 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 10 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw p d power dissipation per output transistor 100 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 3.0 18 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
iw4020b 41 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v -55 c25 c 125 c unit v ih minimum high-level input voltage v out =0.5v or v cc - 0.5v v out =1.0v or v cc - 1.0v v out =1.5v or v cc - 1.5v 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 v v il maximum low -level input voltage v out =0.5v or v cc - 0.5v v out =1.0v or v cc - 1.0v v out =1.5v or v cc - 1.5v 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 v v oh minimum high-level output voltage v in =gnd or v cc 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v ol maximum low-level output voltage v in =gnd or v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i in maximum input leakage current v in = gnd or v cc 18 0.1 0.1 1.0 a i cc maximum quiescent supply current (per package) v in = gnd or v cc 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 a i ol minimum output low (sink) current v in = gnd or v cc u ol =0.4 v u ol =0.5 v u ol =1.5 v 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 ma i oh minimum output high (source) current v in = gnd or v cc u oh =2.5 v u oh =4.6 v u oh =9.5 v u oh =13.5 v 5.0 5.0 10 15 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 ma
iw4020b 42 ac electrical characteristics (c l =50pf, r l =200k ? , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c25 c 125 c unit f max maximum clock frequency(figure 1) 5.0 10 15 3.5 8 12 3.5 8 12 1.75 4 6 mhz t plh , t phl maximum propagation delay, clock to q1 (figure 1) 5.0 10 15 360 160 130 360 160 130 720 320 260 ns t plh , t phl maximum propagation delay, q n to q n +1 (figure 3) 5.0 10 15 330 80 60 330 80 60 660 160 120 ns t phl maximum propagation delay, reset to any q (figure 2) 5.0 10 15 280 120 100 280 120 100 560 240 200 ns t tlh , t thl maximum output transition time, any output (figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns c in maximum input capacitance - 7.5 pf timing requirements (c l =50pf, r l =200k ? , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c25 c 125 c unit t w minimum pulse width, clock (figure 1) 5.0 10 15 140 60 40 140 60 40 280 120 80 ns t w minimum pulse width, reset (figure 2) 5.0 10 15 200 80 60 200 80 60 400 160 120 ns t rem minimum removal time, reset(figure 2) 5.0 10 15 350 150 100 350 150 100 700 300 200 ns t r, t f maximum input rise and fall times, clock (figure 1) 5.0 10 15 unlimited s
iw4020b 43 figure 1. switching waveforms figure 2. switching waveforms figure 3. switching waveforms
iw4020b 44 timing diagram expanded logic diagram
|
